{"id":137,"date":"2021-12-11T00:11:56","date_gmt":"2021-12-10T23:11:56","guid":{"rendered":"https:\/\/zappp.pl\/blog\/?p=137"},"modified":"2023-02-19T23:48:16","modified_gmt":"2023-02-19T22:48:16","slug":"library-1-sterownik-silnika-krokowego-na-stm32f429-disco-part-1","status":"publish","type":"post","link":"https:\/\/www.zappp.pl\/blog\/library-1-sterownik-silnika-krokowego-na-stm32f429-disco-part-1\/","title":{"rendered":"Library 1 \u2013 sterownik silnika krokowego na STM32F429-DISCO (part 1)."},"content":{"rendered":"\n<p class=\"has-drop-cap wp-block-paragraph\"><strong>Niniejszym wpisem chcia\u0142bym zapocz\u0105tkowa\u0107 cykl post\u00f3w opisuj\u0105cych bibliotek\u0119 do zarz\u0105dzania prac\u0105 silnika krokowego. W tej cz\u0119\u015bci zajm\u0119 si\u0119 kr\u00f3tkim opisem projektu, pod\u0142\u0105czeniem silnik-L6258 (p\u0142ytka P46d)-STM32F429_DISCO-PC oraz konfiguracj\u0105 peryferi\u00f3w mikrokontrolera.<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Projekt do pobrania z: <\/strong><a href=\"https:\/\/github.com\/PiotrPoterala\/stm32f429i-disco_stepper_motor\">https:\/\/github.com\/PiotrPoterala\/stm32f429i-disco_stepper_motor<\/a><\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Wykorzystane technologie:<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\"><li>C++11,<\/li><li>RTOS: RTX5.<\/li><\/ul>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Cechy:<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\"><li>Obs\u0142uga driver\u00f3w silnik\u00f3w krokowych dysponuj\u0105cych interfejsem r\u00f3wnoleg\u0142ym opartym na:<ul><li>parze sygna\u0142\u00f3w dir\/clock,<\/li><\/ul><ul><li>parze sygna\u0142\u00f3w zegarowych przesuni\u0119tych w fazie + informacja o poziomie pr\u0105du p\u0142yn\u0105cego przez dane uzwojenie,<\/li><\/ul><\/li><li>Obs\u0142uga interfejsu UART do komunikacji z PC.<\/li><\/ul>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Zale\u017cno\u015bci:<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\"><li>CMSIS,<ul><li>CORE,<\/li><\/ul><ul><li>RTOS2,<\/li><\/ul><\/li><li>PP library: <a href=\"https:\/\/github.com\/PiotrPoterala\/PP_Library\">https:\/\/github.com\/PiotrPoterala\/PP_Library<\/a><\/li><\/ul>\n\n\n\n<h4 class=\"wp-block-heading\">Pod\u0142\u0105czenie systemu:<\/h4>\n\n\n\n<figure class=\"wp-block-image alignwide size-full is-style-default\"><img loading=\"lazy\" decoding=\"async\" width=\"1174\" height=\"754\" src=\"https:\/\/zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/stm32f429disco_P46d_schemat_blokowy2.png\" alt=\"\" class=\"wp-image-138\" srcset=\"https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/stm32f429disco_P46d_schemat_blokowy2.png 1174w, https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/stm32f429disco_P46d_schemat_blokowy2-300x193.png 300w, https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/stm32f429disco_P46d_schemat_blokowy2-1024x658.png 1024w, https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/stm32f429disco_P46d_schemat_blokowy2-768x493.png 768w\" sizes=\"auto, (max-width: 1174px) 100vw, 1174px\" \/><figcaption>Rysunek 1-1<\/figcaption><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Pliki konfiguracyjne (<em>config.h, config.cpp)<\/em>:<\/strong><\/h4>\n\n\n\n<h5 class=\"wp-block-heading\">Konfiguracja zegara<\/h5>\n\n\n\n<h6 class=\"wp-block-heading\">config.cpp<\/h6>\n\n\n\n<pre class=\"wp-block-code has-extra-small-font-size\"><code>void RCC_Config(void){\n\n    SystemInit();\n\t\n    RCC-&gt;CR |= RCC_CR_HSEON;\n    while(!(RCC-&gt;CR &amp; RCC_CR_HSERDY)) \n\t\t\t;\n    RCC-&gt;APB1ENR |= RCC_APB1ENR_PWREN;\n    PWR-&gt;CR |= PWR_CR_VOS;\n\n    RCC-&gt;CR&amp;=~RCC_CR_PLLON;\n    while(RCC-&gt;CR &amp; RCC_CR_PLLRDY);\n    RCC-&gt;PLLCFGR|=RCC_PLLCFGR_PLLSRC;\n    RCC-&gt;PLLCFGR=(RCC-&gt;PLLCFGR &amp; ~RCC_PLLCFGR_PLLM) | RCC_PLLCFGR_PLLM_DIV4;\n    RCC-&gt;PLLCFGR=(RCC-&gt;PLLCFGR &amp; ~RCC_PLLCFGR_PLLN) | RCC_PLLCFGR_PLLN_MUL180;\n    RCC-&gt;PLLCFGR=(RCC-&gt;PLLCFGR &amp; ~RCC_PLLCFGR_PLLP) | RCC_PLLCFGR_PLLP_DIV2;\n    RCC-&gt;CR|=RCC_CR_PLLON;\n    while(!(RCC-&gt;CR &amp; RCC_CR_PLLRDY)) \n\t\t\t;\n\t\n   \n    PWR-&gt;CR |= PWR_CR_ODEN;\n    while(!(PWR-&gt;CSR &amp; PWR_CSR_ODRDY));\n    PWR-&gt;CR |= PWR_CR_ODSWEN;\n    while(!(PWR-&gt;CSR &amp; PWR_CSR_ODSWRDY));    \n\n    FLASH-&gt;ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;\n\n    RCC-&gt;CFGR=(RCC-&gt;CFGR &amp; ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;\n    RCC-&gt;CFGR |= RCC_CFGR_HPRE_DIV1;\n    RCC-&gt;CFGR |= RCC_CFGR_PPRE2_DIV2;\n    RCC-&gt;CFGR |= RCC_CFGR_PPRE1_DIV4;\n\n    \/* Wait till the main PLL is used as system clock source *\/\n    while ((RCC-&gt;CFGR &amp; (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);\n\n    SystemCoreClockUpdate();\n\t\t\n    RCC-&gt;AHB1ENR |= RCC_AHB1ENR_GPIOAEN;\n    RCC-&gt;AHB1ENR |= RCC_AHB1ENR_GPIOCEN;\t\n    RCC-&gt;AHB1ENR |= RCC_AHB1ENR_GPIODEN;\n    RCC-&gt;AHB1ENR |= RCC_AHB1ENR_GPIOEEN;\t\n    RCC-&gt;AHB1ENR |= RCC_AHB1ENR_GPIOGEN;\n\t\t\n    RCC-&gt;APB2ENR|=RCC_APB2ENR_USART1EN;\n}<\/code><\/pre>\n\n\n\n<p class=\"wp-block-paragraph\">W powy\u017cszym przyk\u0142adzie brak Standard Peripheral Library od ST. Uwa\u017cam, \u017ce wspomniana biblioteka wprowadza zbyt du\u017co niepotrzebnych \u201ezawi\u0142o\u015bci\u201d w postaci konieczno\u015bci tworzenia nikomu niepotrzebnych struktur do zainicjowania konkretnych peryferi\u00f3w. Du\u017co czytelniejszym wydaje mi si\u0119 operowanie \u201ebezpo\u015brednio\u201d na rejestrach (z wykorzystaniem biblioteki CMSIS-CORE), tym bardziej, \u017ce w \u201emanualach\u201d s\u0105 one naprawd\u0119 dobrze opisane. Konfiguracja zegara jest jednak bodaj jedynym miejscem, gdzie wspieram si\u0119 CubeMX\u2019em \u2013 jest fajnym kalkulatorem warto\u015bci poszczeg\u00f3lnych mno\u017cnik\u00f3w i dzielnik\u00f3w sygna\u0142u zegarowego. Zaznaczamy z jakiego \u017ar\u00f3d\u0142a b\u0119dziemy pobiera\u0107 sygna\u0142 zegarowy (tutaj z kwarcu o cz\u0119stotliwo\u015bci rezonansu 8MHz). W <em>PLL Source Mux <\/em>wybieramy HSE, w <em>System Clock Mux<\/em> PLLCLK, nast\u0119pnie w okienku HCLK wpisujemy maksymaln\u0105 cz\u0119stotliwo\u015b\u0107 taktowania rdzenia (tutaj 180MHz), po czym wciskamy <em>Enter<\/em> i nast\u0119puje przeliczenie wszystkich warto\u015bci mno\u017cnik\u00f3w\/dzielnik\u00f3w.<\/p>\n\n\n\n<figure class=\"wp-block-image alignwide size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"773\" src=\"https:\/\/zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/schemat_zegara-1024x773.png\" alt=\"\" class=\"wp-image-140\" srcset=\"https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/schemat_zegara-1024x773.png 1024w, https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/schemat_zegara-300x226.png 300w, https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/schemat_zegara-768x580.png 768w, https:\/\/www.zappp.pl\/blog\/wp-content\/uploads\/2021\/12\/schemat_zegara.png 1102w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<h5 class=\"wp-block-heading\">Konfiguracja GPIO<\/h5>\n\n\n\n<p class=\"wp-block-paragraph\">Wszystkie wyj\u015bcia skonfigurowane jako wyj\u015bcia typu push-pull. Jedynym wyj\u0105tkiem jest pin PD7 pod\u0142\u0105czony do wej\u015bcia *EN p\u0142ytki P46d skonfigurowany jako \u201eotwarty kolektor\u201d. PA9 oraz PA10 ustawione zosta\u0142y jako wej\u015bcia\/wyj\u015bcia alternatywne (w tym przypadku obs\u0142uguj\u0105 linie TX, RX komunikacji USART).<\/p>\n\n\n\n<h6 class=\"wp-block-heading\">config.h<\/h6>\n\n\n\n<pre class=\"wp-block-code has-extra-small-font-size\"><code>\/**\n * Keil project for stepper motor driver\n \n * @author  Piotr Potera\u0142a\n * @email   poterala.piotr@gmail.com\n * @website http:\/\/zappp.pl\n * @version v1.0\n * @ide     Keil uVision 5\n * @license GNU GPL v3\n *\t\n@verbatim\n   ----------------------------------------------------------------------\n    Copyright (C) Piotr Potera\u0142a, 2021c\n    \n    This program is free software: you can redistribute it and\/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    any later version.\n     \n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n    \n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see &lt;http:\/\/www.gnu.org\/licenses\/&gt;.\n   ----------------------------------------------------------------------\n@endverbatim\n *\/\n#ifndef _CONFIG_H\n\t#define _CONFIG_H\n\n\t#include \"stm32xx.h\"\n\n\t#define NVIC_PriGroup_0         ((uint32_t)0x7) \/*!&lt; 0 bits for pre-emption priority\t bits for subpriority *\/\n\t#define NVIC_PriGroup_1         ((uint32_t)0x6) \/*!&lt; 1 bits for pre-emption priority\t3 bits for subpriority *\/\n\t#define NVIC_PriGroup_2         ((uint32_t)0x5) \/*!&lt; 2 bits for pre-emption priority\t2 bits for subpriority *\/\n\t#define NVIC_PriGroup_3         ((uint32_t)0x4) \/*!&lt; 3 bits for pre-emption priority\t1 bits for subpriority *\/\n\t#define NVIC_PriGroup_4         ((uint32_t)0x3) \/*!&lt; 4 bits for pre-emption priority 0 bits for subpriority *\/\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t0 bits for subpriority *\/\n\t#define RCC_PLLCFGR_PLLN_V40\t0x2800\n\t#define RCC_PLLCFGR_PLLR_V2\t\t0x0\n\t#define RCC_PLLCFGR_PLLM_V2\t\t0x10\n\t\n\t#define RCC_PLLCFGR_PLLM_DIV4\t\t\t4\n\t#define RCC_PLLCFGR_PLLN_MUL180\t\t(180&lt;&lt;6)\n\t#define RCC_PLLCFGR_PLLP_DIV2\t\t\t0x0\n\t\n\n\t#define  USART_BSTOP_CLR   0xCFFF           \n\t#define  USART_BSTOP_1     0x0000          \n\t#define  USART_BSTOP_2     0x2000  \n\n\n\t#define GPIO_AFR_AF0\t\t\t\t0x0\n\t#define GPIO_AFR_AF1\t\t\t\t0x1\n\t#define GPIO_AFR_AF2\t\t\t\t0x2\n\t#define GPIO_AFR_AF3\t\t\t\t0x3\n\t#define GPIO_AFR_AF4\t\t\t\t0x4\n\t#define GPIO_AFR_AF5\t\t\t\t0x5\n\t#define GPIO_AFR_AF6\t\t\t\t0x6\n\t#define GPIO_AFR_AF7\t\t\t\t0x7\n\t#define GPIO_AFR_AF8\t\t\t\t0x8\n\t#define GPIO_AFR_AF9\t\t\t\t0x9\n\t#define GPIO_AFR_AF10\t\t\t\t0xA\n\t#define GPIO_AFR_AF11\t\t\t\t0xB\n\t#define GPIO_AFR_AF12\t\t\t\t0xC\n\t#define GPIO_AFR_AF13\t\t\t\t0xD\n\t#define GPIO_AFR_AF14\t\t\t\t0xE\n\t#define GPIO_AFR_AF15\t\t\t\t0xF\n\n\t#define IO_SET_REG1(REG, PIN, SETS) ((REG &amp; ~(0x1&lt;&lt;(PIN))) | ((SETS)&lt;&lt;(PIN)))\n\t#define IO_SET_REG2(REG, PIN, SETS) ((REG &amp; ~(0x3&lt;&lt;(PIN*2))) | ((SETS)&lt;&lt;(PIN*2)))\n        #define IN_SET_REG(REG, PIN, SETS) (REG-&gt;MODER=IO_SET_REG2(REG-&gt;MODER, PIN, IO_IN), REG-&gt;PUPDR=IO_SET_REG2(REG-&gt;PUPDR, PIN, SETS))\n\n        #define OUT_SET_REG(REG, PIN, TYPE, SPEED) (REG-&gt;MODER=IO_SET_REG2(REG-&gt;MODER, PIN, IO_OUT), REG-&gt;OTYPER=IO_SET_REG1(REG-&gt;OTYPER, PIN, TYPE), REG-&gt;OSPEEDR=IO_SET_REG2(REG-&gt;OSPEEDR, PIN, SPEED))\n        #define ALT_SET_REG(REG, PIN, SPEED) (REG-&gt;MODER=IO_SET_REG2(REG-&gt;MODER, PIN, IO_ALT), REG-&gt;OTYPER&amp;=~(1&lt;&lt;PIN), REG-&gt;OSPEEDR=IO_SET_REG2(REG-&gt;OSPEEDR, PIN, SPEED))\n\n\tvoid RCC_Config(void);\n\tvoid NVIC_Config(void);\n\tvoid GPIO_Config(void);\n\tvoid USART_Config(void);\n\n#endif<\/code><\/pre>\n\n\n\n<h6 class=\"wp-block-heading\">config.cpp<\/h6>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:100%\">\n<pre class=\"wp-block-code has-extra-small-font-size\"><code>void GPIO_Config(void)\n{\n\/\/port A\n\tALT_SET_REG(GPIOA, Pin9, IO_OUT_HS);\n\tGPIOA-&gt;AFR&#91;1]=(GPIOA-&gt;AFR&#91;1] &amp; ~(0xF&lt;&lt;((Pin9-8)*4))) | (GPIO_AFR_AF7&lt;&lt;((Pin9-8)*4)); \/\/USART1 TX\n\tALT_SET_REG(GPIOA, Pin10, IO_OUT_HS);\n\tGPIOA-&gt;AFR&#91;1]=(GPIOA-&gt;AFR&#91;1] &amp; ~(0xF&lt;&lt;((Pin10-8)*4))) | (GPIO_AFR_AF7&lt;&lt;((Pin10-8)*4));\t\/\/USART1 RX\n\t\n\/\/port C\n\tOUT_SET_REG(GPIOC, Pin11, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOC, Pin12, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOC, Pin13, IO_PP, IO_OUT_HS);\n\n\/\/port D\n\tOUT_SET_REG(GPIOD, Pin2, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOD, Pin4, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOD, Pin5, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOD, Pin7, IO_OD, IO_OUT_HS);\n\n\/\/port E\t\n\tOUT_SET_REG(GPIOE, Pin2, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOE, Pin3, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOE, Pin4, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOE, Pin5, IO_PP, IO_OUT_HS);\n\tOUT_SET_REG(GPIOE, Pin6, IO_PP, IO_OUT_HS);\n\n\n\/\/port G\t\n\tOUT_SET_REG(GPIOG, Pin13, IO_PP, IO_OUT_HS);\t\/\/LED1\n\tOUT_SET_REG(GPIOG, Pin14, IO_PP, IO_OUT_HS);\t\/\/LED2\n\t\n\t\n\t\n\tPIN_CLR(PORT_LED, LED1);\n\tPIN_CLR(PORT_LED, LED2);\n\n}<\/code><\/pre>\n<\/div>\n<\/div>\n\n\n\n<h5 class=\"wp-block-heading\">Konfiguracja USART<\/h5>\n\n\n\n<p class=\"wp-block-paragraph\">USART skonfigurowany zosta\u0142 tak aby:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Ramka sk\u0142ada\u0142a si\u0119 z: 8 bit\u00f3w danych, 1 bitu stopu, bez parzysto\u015bci,<\/li><li>Pr\u0119dko\u015b\u0107 transmisji wynosi\u0142a 9600 bod\u00f3w na sekund\u0119<\/li><\/ul>\n\n\n\n<h6 class=\"wp-block-heading\">config.cpp<\/h6>\n\n\n\n<pre class=\"wp-block-code has-black-color has-text-color has-extra-small-font-size\"><code>void USART_Config(void){\n\tdouble divider = 0x00;\n\t\n\tUSART1-&gt;CR1&amp;=~USART_CR1_PCE;\t\t\/\/parity: no\t\t\n\tUSART1-&gt;CR1&amp;=~USART_CR1_M;\t\t\t\/\/8 data bits\n\tUSART1-&gt;CR2=(USART1-&gt;CR2 &amp; USART_BSTOP_CLR) | USART_BSTOP_1;\t\t\t\/\/1 stop bit\n\n\tUSART1-&gt;CR1&amp;=~USART_CR1_OVER8; \/\/oversampling=16 \n\n  divider = ((double)90000000 \/ (16*9600));\t\t\/\/PLCK1\/(16*BAUD) for oversampling=16    \n  USART1-&gt;BRR |= (uint16_t)divider &lt;&lt; 4;\n  USART1-&gt;BRR |= (uint16_t)((divider-(uint16_t)divider)*16);\n\n\tUSART1-&gt;CR1|=USART_CR1_TE;\n\tUSART1-&gt;CR1&amp;=~USART_CR1_TXEIE;\n\tUSART1-&gt;CR1|=USART_CR1_RE;\n\tUSART1-&gt;CR1|=USART_CR1_RXNEIE;\n\tUSART1-&gt;CR1|=USART_CR1_UE;\t\n\n}<\/code><\/pre>\n","protected":false},"excerpt":{"rendered":"<p>Niniejszym wpisem chcia\u0142bym zapocz\u0105tkowa\u0107 cykl post\u00f3w opisuj\u0105cych bibliotek\u0119 do zarz\u0105dzania prac\u0105 silnika krokowego. W tej cz\u0119\u015bci zajm\u0119 si\u0119 kr\u00f3tkim opisem projektu, pod\u0142\u0105czeniem silnik-L6258 (p\u0142ytka P46d)-STM32F429_DISCO-PC oraz konfiguracj\u0105 peryferi\u00f3w mikrokontrolera. Projekt do pobrania z: https:\/\/github.com\/PiotrPoterala\/stm32f429i-disco_stepper_motor Wykorzystane technologie: C++11, RTOS: RTX5. Cechy: Obs\u0142uga driver\u00f3w silnik\u00f3w krokowych dysponuj\u0105cych interfejsem r\u00f3wnoleg\u0142ym opartym na: parze sygna\u0142\u00f3w dir\/clock, parze sygna\u0142\u00f3w zegarowych&hellip; <a class=\"more-link\" href=\"https:\/\/www.zappp.pl\/blog\/library-1-sterownik-silnika-krokowego-na-stm32f429-disco-part-1\/\">Czytaj dalej <span class=\"screen-reader-text\">Library 1 \u2013 sterownik silnika krokowego na STM32F429-DISCO (part 1).<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[5],"tags":[7,8,9,10,6],"class_list":["post-137","post","type-post","status-publish","format-standard","hentry","category-stm32f429-disco","tag-disco","tag-l6258","tag-p46d","tag-stepper-motor-driver","tag-stm32f429","entry"],"_links":{"self":[{"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/posts\/137","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/comments?post=137"}],"version-history":[{"count":9,"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/posts\/137\/revisions"}],"predecessor-version":[{"id":202,"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/posts\/137\/revisions\/202"}],"wp:attachment":[{"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/media?parent=137"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/categories?post=137"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.zappp.pl\/blog\/wp-json\/wp\/v2\/tags?post=137"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}